Embedded Flash Memory; Embedded Sram Memory; Ahb Peripherals; Apb Peripherals - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

Embedded Flash Memory

The HT32F12345 device provides 64 KB on-chip Flash memory which is located at address
0x0000_0000. It supports bytes, halt-words and word access. Note that Flash memory only
supports read operation for Cortex
Flash memory (via DCode bus) will cause a bus fault exception. The Flash memory has a capacity
of 64 pages. Each page has a memory capacity of 1 KB and can be erased independently. A 32-
bit programming interface provides the capability of changing bits from 1 to 0. A data storage or
firmware upgrade can be implemented using several methods such as In System Programming (ISP),
In Application Programming (IAP) or In Circuit Programming (ICP). The above programming
methods provide flexibility to user for data storage and firmware upgrade purpose. For more
information, refer to the Flash Memory Controller section.

Embedded SRAM Memory

The HT32F12345 device contains up to 16 KB on-chip SRAM which is located at address
0x2000_0000. It supports bytes, half-words and full words access operations. In order to reduce
the time of read-modify-write operations, the Cortex
perform a single atomic bit operation. Users can modify a single bit in SRAM bit-band region by
accessing the corresponding bit-band alias. For more information about bit-binding, refer to the
Arm ® Cortex ® -M3 Technical Reference Manual. The following formulas and examples show how
to access a bit in the bit-band region by calculate the bit-band alias.
Bit-band alias = Bit-band base + (byte offset × 32) + (bit number × 4)
For example, if you want to access bit 7 of address 0x2000_0200, the bit-band alias is:
Bit-band alias = 0x2200_0000 + (0x200 × 32) + (7 × 4) = 0x2200_401C
Write to address 0x2200_401C causes the bit 7 of address 0x2000_0200 changed. On the contrary,
read address 0x2200_401C returns 0x01 or 0x00 according to the value of bit 7 at SRAM address
0x2000_0200.

AHB Peripherals

The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF. Some peripherals
such as Clock Control Unit, Reset Control Unit and Flash Memory Controller are connected to the
AHB bus directly. The AHB peripheral clocks are always enabled after system reset. Access to
registers for these peripherals can be achieved directly via the AHB bus. Note that all peripheral
registers in AHB bus support only word access.

APB Peripherals

The address of APB peripherals ranges from 0x4000_0000 to 0x4007_FFFF. An APB to AHB
bridge provides access capability between the Cortex
the APB peripheral clocks are disabled after a system reset. Software must enable peripheral clock
by setting up the APBCCRn registers in Clock Control Unit before accessing the corresponding
peripheral register. Note that the APB to AHB bridge will duplicate the half-word or byte data
to word width when a half-word or byte access is performed on APB peripheral register. In other
words, the access result of half-word or byte access on APB peripheral register will vary depending
on the data bit width of the access operation on the peripheral registers.
Rev. 1.10
® -M3 ICode or DCode bus access. Any write operation to the
® -M3 provides a bit-banding function to
® -M3 and the APB peripherals. Additionally,
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