Memory Organization; Figure 3. Bus Architecture - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Cortex
Processor
NVIC

Figure 3. Bus Architecture

Memory Organization

The Arm ® Cortex
interface to external AHB peripheral. The processor accesses take priority over debug accesses.
The maximum address range of the Cortex
Additionally, a pre-defined memory map is provided by the Cortex
the software complexity of repeated implementation of different device vendors. However, some
regions are used by the Arm
Technical Reference Manual for more information. The following figure shows the memory map
of HT32F52220/HT32F52230 series of devices, including Code, SRAM, peripheral, and other pre-
defined regions.
Rev. 1.10
GPIO
®
-M0+
® -M0+ processor accesses and debug accesses share the single external
® Cortex ® -M0+ system peripherals. Refer to the Arm
26 of 366
Flash Memory
Interface
FMC
Control Registers
AHB Peripherals
SRAM Controller
AHB to APB
Bridge
® -M0+ is 4 GB since it has 32-bit bus address width.
-M0+ processor to reduce
®
Flash
Memory
CKCU/RSTCU
Control Registers
SRAM
APB IPs
® Cortex ® -M0+
November 09, 2018