Bus Architecture; Figure 2. Cortex ® -M0+ Block Diagram - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Cortex
Interrupts
Controller (WIC)
‡ Optional Componect
Figure 2. Cortex -M0+ Block Diagram
®

Bus Architecture

The HT32F52220/HT32F52230 series consists of one master and four slaves in the bus architecture.
The Cortex ® -M0+ AHB-Lite bus is the master while the internal SRAM access bus, the internal
Flash memory access bus, the AHB peripherals access bus and the AHB to APB bridges are the
slaves. The single 32-bit AHB-Lite system interface provides simple integration to all system
regions include the internal SRAM region and the peripheral region. All of the master buses are
based on 32-bit Advanced High-performance Bus-Lite (AHB-Lite) protocol. The following figure
shows the bus architecture of the HT32F52220/HT32F52230 series.
Rev. 1.10
®
-M0+ Components
Execution Trace Interface
Cortex-M0+ Processor
Nested
Vectored
Interrupt
Controller
(NVIC)
‡ Wakeup
Interrupt
25 of 366
Debug
‡ Breakpoint
Cortex -M0+
®
and
Processor
Watchpoint
Core
Unit
‡ Memory
‡ Debugger
Protection
Interface
Unit
Bus Matrix
AHB-Lite Interface ‡ Single-cycle
to System I/O Port
‡ Debug
Access Port
(DAP)
‡ Serial Wire or JTAG
Debug Port
November 09, 2018