Timer Trigger Configuration Register - Trcfr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Timer Trigger Configuration Register – TRCFR
This register specifies the GPTM external clock setting and the trigger source selection.
Offset: 0x008
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Reserved
Type/Reset
7
Type/Reset
Bits Field
[24] ECME
[16] ETIPOL
[13:12] ETIPSC
Rev. 1.10
30 29 28
Reserved
22 21 20
Reserved
14 13 12
ETIPSC
RW 0 RW
6 5 4
Reserved
Descriptions
External Clock Mode Enable
0: External clock mode is disabled
1: External clock mode is enabled
Setting the ECME bit has the same effect as configuring STI trigger slave mode in
which the trigger source is derived from the GTn_ETI pin, the external clock input on
the GTn_ETI pin is used.
External Trigger Polarity
0: GTn_ETI active at high level or rising edge
1: GTn_ETI active at low level or falling edge
External Trigger Prescaler
A prescaler can be enabled to reduce the ETIP frequency.
00: Prescaler OFF
01: ETIP frequency divided by 2
10: ETIP frequency divided by 4
11: ETIP frequency divided by 8
255 of 590
27 26
19 18
11 10
0 RW 0 RW 0 RW
3 2
RW 0 RW 0 RW
25 24
ECME
RW 0
17 16
ETIPOL
RW 0
9 8
ETF
0 RW 0
1 0
TRSEL
0 RW 0
November 28, 2018