Adc Interrupt Clear Register - Adciclr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
ADC Interrupt Clear Register – ADCICLR
This register provides the clear bits used to clear the interrupt raw and interrupt status of the ADC. These bits are
set to 1 by software to clear the interrupt status and automatically cleared to 0 by hardware after being set to 1.
Offset: 0x13C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[25] ADICLRHO
[24] ADICLRO
[17] ADICLRU
[16] ADICLRL
[10] ADICLRHC
[9] ADICLRHG
[8] ADICLRHS
[2] ADICLRC
[1] ADICLRG
[0] ADICLRS
Rev. 1.10
30 29 28
Reserved
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved
Descriptions
ADC High Priority Data Register Overwrite Interrupt Status Clear Bit
0: No effect
1: Clear ADIEHO
ADC Regular Data Register Overwrite Interrupt Status Clear Bit
0: No effect
1: Clear ADIEO
ADC Watchdog Upper Threshold Interrupt Status Clear Bit
0: No effect
1: Clear ADIEU
ADC Watchdog Lower Threshold Interrupt Status Clear Bit
0: No effect
1: Clear ADIEL
ADC High Priority Cycle EOC Interrupt Status Clear Bit
0: No effect
1: Clear ADIEHC
ADC High Priority Subgroup EOC Interrupt Status Clear Bit
0: No effect
1: Clear ADIEHG
ADC High Priority Single EOC Interrupt Status Clear Bit
0: No effect
1: Clear ADIEHS
ADC Regular Cycle EOC Interrupt Status Clear Bit
0: No effect
1: Clear ADIEC
ADC Regular Subgroup EOC Interrupt Status Clear Bit
0: No effect
1: Clear ADIEG
ADC Regular Single EOC Interrupt Status Clear Bit
0: No effect
1: Clear ADIES
213 of 590
27 26 25
ADICLRHO ADICLRO
WO
19 18 17
ADICLRU
WO
11 10 9
ADICLRHC ADICLRHG ADICLRHS
WO 0 WO
3 2 1
ADICLRC ADICLRG
WO 0 WO
November 28, 2018
24
0 WO 0
16
ADICLRL
0 WO 0
8
0 WO 0
0
ADICLRS
0 WO 0