Adc Watchdog Control Register - Adcwcr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
ADC Watchdog Control Register – ADCWCR
This register provides the control bits and status of the ADC watchdog function.
Offset: 0x078
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[27:24] ADUCH
[19:16] ADLCH
[11:8] ADWCH
[2] ADWALL
Rev. 1.10
30 29 28
Reserved
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Upper Threshold Channel Status
0000: ADC_IN0 converted data is higher than the upper threshold
0001: ADC_IN1 converted data is higher than the upper threshold
...
1011: ADC_IN7 converted data is higher than the upper threshold
Others: Reserved
If one of these status bits is set to 1 by the watchdog monitor function, the status
field value should first be stored in the user-defined memory location in the
corresponding ISR. Otherwise, the ADUCH field will be changed if another input
channel converted data is higher than the upper threshold.
Lower Threshold Channel Status
0000: ADC_IN0 converted data is lower than the lower threshold
0001: ADC_IN1 converted data is lower than the lower threshold
...
1011: ADC_IN7 converted data is lower than the lower threshold
Others: Reserved
If one of these status bits is set to 1 by the watchdog monitor function, the status
field value should first be stored in the user-defined memory location in the
corresponding ISR. Otherwise, the ADLCH field will be changed if another input
channel converted data is lower than the lower threshold.
ADC Watchdog Specific Channel Selection
0000: ADC_IN0 is monitored
0001: ADC_IN1 is monitored
...
1011: ADC_IN7 is monitored
Others: Reserved
ADC Watchdog Specific or All Channel Setting
0: Only the channel which specified by the ASWCH field is monitored
1: All channels are monitored
169 of 366
27 26
ADUCH
RO 0 RO 0 RO
19 18
ADLCH
RO 0 RO 0 RO
11 10
ADWCH
RW 0 RW 0 RW
3 2
ADWALL ADWUE
RW 0 RW
25 24
0 RO 0
17 16
0 RO 0
9 8
0 RW 0
1 0
ADWLE
0 RW 0
November 09, 2018