Load And Store Alignment - IBM PPC440X5 CPU Core User Manual

Preliminary
Once a data cache line read request has been made, the entire line read will be performed and the line will be
written into the data cache, regardless of whether or not the instruction stream branches (or is interrupted)
away from the instruction which prompted the initial line read request. That is, if a data cache line read is initi-
ated speculatively, before knowing whether or not a given instruction execution is really required (for
example, on a load instruction which is after an unresolved branch), that line read will be completed, even if it
is later determined that the cache line is not really needed. The DCC never aborts any PLB request once it
has been made, except when a processor reset occurs while the PLB request is being made.
In general, the DCC will initiate memory read requests without waiting to determine whether the access is
actually required by the sequential execution model (SEM). That is, the request will be initiated speculatively,
even if the instruction causing the request might be abandoned due to a branch, interrupt, or other change in
the instruction flow. Of course, write requests to memory cannot be initiated speculatively, although a line fill
request in response to a cacheable store access which misses in the data cache could be.
On the other hand, if the guarded storage attribute is set for the memory page being accessed, then the
memory request will not be initiated until it is guaranteed that the access is required by the SEM. Once initi-
ated, the access will not be abandoned, and the instruction is guaranteed to complete, prior to any change in
the instruction stream. That is, if the instruction stream is interrupted, then upon return the instruction execu-
tion will resume after the instruction which accessed guarded storage, such that the guarded storage access
will not be re-executed.
See Guarded (G) on page 146 for more information on accessing guarded storage.
Programming Note:
It is a programming error for a load, store, or dcbz instruction to reference a valid cache line in
the data cache if the caching inhibited storage attribute is set for the memory page containing the
cache line. The result of such an access is undefined. After processor reset, hardware
automatically sets the caching inhibited storage attribute for the memory page containing the
reset address, and software should flash invalidate the data cache (using dccci; see Data Cache
Management and Debug Instruction Summary on page 125) before executing any load, store, or
dcbz instructions. Subsequently, lines will not be placed into the data cache unless they are
accessed by reference to a memory page for which the caching inhibited attribute has been
turned off. If software subsequently turns on the caching inhibited storage attribute for such a
page, software must make sure that no lines from that page remain valid in the data cache
(typically by using the dcbf instruction), before attempting to access the (now caching inhibited)
page with load, store, or dcbz instructions.
The only instructions that are permitted to reference a caching inhibited line which is a hit in the
data cache are the cache management instructions dcbst, dcbf, dcbi, dccci, and dcread. The
dcbt and dcbtst instructions have no effect if they reference a caching inhibited address,
regardless of whether the line exists in the data cache.

4.3.1.1 Load and Store Alignment

The DCC implements all of the integer load and store instructions defined for 32-bit implementations by the
PowerPC Book-E architecture. These include byte, halfword, and word loads and stores, as well as load and
store string (0 to 127 bytes) and load and store multiple (1 to 32 registers) instructions. Integer byte, halfword,
and word loads and stores are performed with a single access to memory if the entire data operand is
contained within an aligned 16-byte (quadword) block of memory, regardless of the actual operand alignment
within that block. If the data operand crosses a quadword boundary, the load or store is performed using two
accesses to memory.
cache.fm.
September 12, 2002
User's Manual
PPC440x5 CPU Core
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