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User's Manual
A2 Processor
Figure 1-2. A2 Processor Block Diagram
A2 Core
AXU
Interface
Data
Cache
Unit
CR
1.4.7.1 Arithmetic and Load/Store Pipelines
The A2 core has a single execution pipeline. The pipeline handles all computational instructions and reads
from and writes to the FPRs, Floating-Point Status and Control Register (FPSCR), and the Condition Register
(CR).
1.4.8 IEEE 754 and Architectural Compliance
The A2 core is IEEE 754 and Power ISA compliant and implements single-precision and double-precision
instructions.
Overview
Page 56 of 864
Floating-Point AXU
Instruction Decode/Issue Unit
Thread 0
Thread 1
Load/Store
Pipe
Thread 2
FPR0
FPR1
FPR1
•
Arithmetic
•
•
FPR30
FPR31
FPSCR
Thread 3
Pipe
Version 1.3
October 23, 2012
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