Processor And Cache; P5-550Q Power5+ Quad-Core Module - IBM System p5 550 Technical Overview And Introduction

Double the SMP support. Changes have been made in the fabric, L2 and L3 controller,
memory controller, GX+ controller, and chip RAS to provide support for the QCM
(quad-core module) that allows the SMP system sizes to be double than is available in
POWER5 DCM-based servers. Current POWER5+ implementations support only a single
address loop.
Several enhancements have been made in the memory controller for improved
performance. The memory controller is ready to support DDR2 667 MHz DIMMs in the
future.
Enhanced redundancy in L1 Dcache, L2 cache, and L3 directory. Independent control of
the L2 cache and the L3 directory for redundancy to allow split-repair action has been
added. More wordline redundancy has been added in the L1 Dcache. In addition, Array
Built-In Self Test (ABIST) column repair for the L2 cache and the L3 directory has been
added.

2.2 Processor and cache

In the p5-550 or p5-550Q, the POWER5+ processors, associated L3 cache chips, and
memory DIMMs are packaged in processor cards. The POWER5+ processor and L3 cache
chips are packaged into POWER5+ processor modules. The p5-550 or p5-550Q use different
POWER5+ processor modules. The p5-550 uses a dual-core module (DCM) while the
p5-550Q uses an enhanced new packaging: the quad-core module (QCM).

2.2.1 p5-550Q POWER5+ quad-core module

The 4-core p5-550Q processor card contains a new POWER5+ quad-core module (QCM)
and the local memory storage subsystem for that QCM. Two POWER5+ dual core chips and
their associated L3 cache chips are packaged in the QCM. Figure 2-3 shows a layout view of
a QCM with associated memory.
Figure 2-3 p5-550Q POWER5+ 1.65 GHz QCM processor card with DDR2 memory socket layout view
The storage structure for the POWER5+ processor is a distributed memory architecture that
provides high-memory bandwidth. Each processor in the QCM can address all memory and
sees a single shared memory resource. In the QCM, one POWER5+ processor has direct
access to eight memory slots, controlled by two SMI-II chips, which are located in close
physical proximity to the processor modules. The other POWER5+ processor has access to
the same memory slots through the Vertical Fabric Bus.
2x 8B 2x 8B
@528 MHz @528 MHz
DIMM DIMM
DIMM DIMM
1056 MHz 1056 MHz
DIMM DIMM
2 x 8B for read 2 x 8B for read
2 x 2B for write 2 x 2B for write
DIMM DIMM
DIMM DIMM
DIMM DIMM
DIMM DIMM
DIMM DIMM
QCM QCM
Core Core
1.65 GHz 1.65 GHz
36 MB 36 MB
2 x 16B 2 x 16B
L3 cache L3 cache
L3 L3
@825 MHz @825 MHz
ctrl ctrl
Mem Mem
ctrl ctrl
Mem Mem
ctrl ctrl
2 x 16B 2 x 16B
L3 L3
36 MB 36 MB
ctrl ctrl
@825 MHz @825 MHz
L3 cache L3 cache
Core Core
1.65 GHz 1.65 GHz
Chapter 2. Architecture and technical overview
GX+ GX+
GX+ GX+ GX+
Bus Bus
Core Core
Ctrl Ctrl Ctrl
1.65 GHz 1.65 GHz
1.9 MB 1.9 MB
L2 cache L2 cache
Enhanced Enhanced
distributed switch distributed switch
Enhanced Enhanced
distributed switch distributed switch
1.9 MB 1.9 MB
L2 cache L2 cache
Core Core
GX+ GX+ GX+
1.65 GHz 1.65 GHz
Ctrl Ctrl Ctrl
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