Cache Inhibit (Ci)-Output; Write-Through (Wt)-Output - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
7.2.4.4 Cache Inhibit (CI)—Output
The cache inhibit (CI) signal is an output signal on the 750GX.
State Asserted
Negated
Timing Assertion/
Negation/
High
Impedance
7.2.4.5 Write-Through (WT)—Output
The write-through (WT) signal is an output signal on the 750GX.
State Asserted
Negated
Timing Assertion/
Negation/
High
Impedance
Signal Descriptions
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Indicates that a single-beat transfer will not be cached, reflecting the setting
of the I bit for the block or page that contains the address of the current
transaction.
Indicates that a burst transfer will allocate the 750GX data-cache block.
The same as A[0–31].
Indicates that a single-beat write transaction is write-through, reflecting the
value of the W bit for the block or page that contains the address of the
current transaction. Assertion during a read operation indicates a data load.
Indicates that a write transaction is not write-through. During a read opera-
tion, negation indicates an instruction load.
The same as A[0–31].
gx_07.fm.(1.2)
March 27, 2006