Coherency Between Cache And External Memory; Prefetch Operation - Hitachi SH7750 Programming Manual

4.3.8

Coherency between Cache and External Memory

Coherency between cache and external memory should be assured by software. In the SH7750, the
following four new instructions are supported for cache operations. For details of these
instructions, see section 10, Instruction Descriptions.
Invalidate instruction:
Purge instruction:
Write-back instruction:
Allocate instruction:
4.3.9

Prefetch Operation

The SH7750 supports a prefetch instruction to reduce the cache fill penalty incurred as the result
of a cache miss. If it is known that a cache miss will result from a read or write operation, it is
possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a
cache miss due to the read or write operation, and so improve software performance. If a prefetch
instruction is executed for data already held in the cache, or if the prefetch address results in a
UTLB miss or a protection violation, the result is no operation, and an exception is not generated.
For details of the prefetch instruction, see section 10.74, PREF.
Prefetch instruction:
OCBI @Rn
OCBP @Rn
OCBWB @Rn
MOVCA.L R0,@Rn
PREF @Rn
Cache invalidation (no write-back)
Cache invalidation (with write-back)
Cache write-back
Cache allocation
Rev. 2.0, 03/99, page 71 of 396