Samsung S5PC110 Manual page 1867

S5PC110_UM
3.7.1.1 IIS-BUS Interface Special Registers (IISCON)
• IISCON, R/W, Address = 0xE210_0000
• IISCON, R/W, Address = 0xE2A0_0000
IISCON
Reserved [31:20]
FRXOFSTATUS
FRXOFINTEN
FTXURSTATUS
FTXURINTEN
Reserved [15:12]
LRI
FTXEMPT
FRXEMPT
FTXFULL
FRXFULL
Bit
Reserved. Program to zero.
[19] RX FIFO OverFlow Interrupt Status. And this is used by
interrupt clear bit. When this is high, you can do interrupt
clear by writing '1'.
0 = Interrupt didn't be occurred.
1 = Interrupt was occurred.
[18] RX FIFO OverFlow Interrupt Enable
0 = RXFIFO Under-run INT disable
1 = RXFIFO Under-run INT enable
[17] TX FIFO under-run interrupt status. And this is used by
interrupt clear bit. When this is high, you can do interrupt
clear by writing '1'.
0 = Interrupt didn't be occurred.
1 = Interrupt was occurred.
[16] TX FIFO Under-run Interrupt Enable
0 = TXFIFO Under-run INT disable
1 = TXFIFO Under-run INT enable
Reserved. Program to zero.
[11] Left/Right channel clock indication. Note that LRI
meaning is dependent on the value of LRP bit of
I2SMOD register.
0 = Left (when LRP bit is low) or right (when LRP bit is
high)
1 = Right (when LRP bit is low) or left (when LRP bit is
high)
[10] Tx FIFO empty status indication.
0 = FIFO is not empty (ready for transmit data to
channel)
1 = FIFO is empty (not ready for transmit data to
channel)
[9] Rx FIFO empty status indication.
0 = FIFO is not empty
1 = FIFO is empty
[8] Tx FIFO full status indication.
0 = FIFO is not full
1 = FIFO is full
[7] Rx FIFO full status indication.
0 = FIFO is not full (ready for receive data from channel)
1 = FIFO is full (not ready for receive data from channel)
Description
3 IIS-BUS INTERFACE
R/W Initial State
R/W 12'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 4'b0
R 1'b1
R 1'b1
R 1'b1
R 1'b0
R 1'b0
3-16