Samsung S5PC110 Manual page 1859

S5PC110_UM
3.5 PROGRAMMING GUIDE
The IIS bus interface can be accessed either by the processor using programmed I/O instructions or by the DMA
controller.
3.5.1 INITIALIZATION
1. Before you use IIS bus interface, you must configure GPIOs to IIS mode, that is, I2SSDI is input and I2SSDO
is output. I2SLRCLK, I2SSCLK and I2SCDCLK is inout-type.
2. Select clock source. S5PC110 has three clock sources, namely, PCLK, EPLL and external codec. For more
information, refer
Figure 3-2.
3.5.2 PLAY MODE (TX MODE) WITH DMA
1. TXFIFO is flushed before operation. If you do not distinguish Master/Slave mode from TX/RX mode, you must
study Master/Slave mode and TX/RX mode. Refer Master/Slave chapter.
2. Configure I2SMOD register and I2SPSR (IIS pre-scaler register).
3. To operate system in stability, the internal TXFIFO should be almost full before transmission. For TXFIFO to
be almost full start DMA operation.
4. IIS bus does not support the interrupt. Therefore, you can only check state by polling through accessing SFR.
5. After TXFIFO is full, then I2SACTIVE must be asserted.
3.5.3 RECORDING MODE (RX MODE) WITH DMA
1. RXFIFO is flushed before operation. Also, if you don't distinguish between Master/Slave mode and TX/RX
mode, you must study Master/Slave mode and TX/RX mode. Refer Master/Slave chapter.
2. Configure I2SMOD register and I2SPSR (IIS pre-scaler register).
3. To operate system in stability, the internal RXFIFO should have at least one data before DMA operation. You
must assert I2SACTIVE before DMA operation.
4. Check RXFIFO state by polling through accessing SFR.
5. If RXFIFO is not empty, start RXDMACTIVE.
3 IIS-BUS INTERFACE
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