Samsung S5PC110 Manual page 1662

Risc microprocessor
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S5PC110_UM
10.3.3.29 Audio Related Packet Register (ACR_LSB2, R/W, Address = 0xFA11_01B0)
ACR_LSB2
ACR_LSB2
10.3.3.30 Audio Related Packet Register (ACR_TXCNT, R/W, Address = 0xFA11_01B4)
ACR_TXCNT
-
ACR_TXCNT
10.3.3.31 Audio Related Packet Register (ACR_TXINTERVAL, R/W, Address = 0xFA11_01B8)
ACR_TXINTERVAL
ACR_TX_INTERVAL
10.3.3.32 Audio Related Packet Register (ACR_CTS_OFFSET, R/W, Address = 0xFA11_01BC)
ACR_CTS_OFFSET
ACR_CTS_OFFSET
Bit
[7:0]
Specifies the alternate CTS least significant byte. For more
information, see ALT_CTS_RATE in ACR_CON register.
Bit
[7:5]
Reserved
[4:0]
If ACR_TX_MODE is '10', the ACR packet will be
transmitted 'ACR_TXCNT + 1' times per VBI period.
ALT_CTS_RATE is also applied. This register is only valid if
ACR_TX_MODE is '10'.
Bit
[7:0]
If ACR_TX_MODE is '10', the ACR packet will be
transmitted ACR_TXCNT times during VBI. This register
specifies the number of cycles between each ACR packets
and avoids continuous transmission in more than 18
packets within single DI band. It is only valid if
ACR_TX_MODE is '10'.
Bit
[7:0]
If 'measured CTS mode' is used, the CTS value will be
measured by counting the TMDS clock for a given duration.
This value is added to measured CTS value. It is 8-bit
signed integer, so subtraction is possible.
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Description
Description
Description
Initial State
0x00
Initial State
0
0x1F
Initial State
0x63
Initial State
0x00
10-53

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