Samsung S5PC110 Manual page 1441

S5PC110_UM
6.3.3.3.20 Auxiliary Host Command Register (MFC_COMMON_CHx_RG_9, R/W, Address = 0xF170_2064 or
0xF170_20A4)
MFC_COMMON_CHx_
RG_9
HOST_WR_ADR
6.3.3.3.21 DPB Configuration Control Register (MFC_COMMON_CHx_RG_10, R/W, Address = 0xF170_2068
or 0xF170_20A8)
MFC_COMMON_CHx_
RG_10
SLICE_IF_ENABLE
CONFIG_DELAY_ENABLE
DISPLAY_DELAY
DMX_DISABLE
DPB_FLUSH
NUM_DPB
Bit
[31:0] The address points to a space of shared memory
consisting of multiple commands which host can
read/write.
The detailed structure of the shared memory is described
in chapter 6.4
Bit
[31] Enable slice interface for decoding
0 = Disable
1 = Enable
[30] Enable configurable display delay for H.264 decoding
0 = Disable
1 = Enable
[29:16] Number of frames for display delay. MFC is forced to
return frames for display even if DPB is not filled. It is
valid for H.264 decoder only.
[15] Host may generate the descriptor information on
behalf of MFC demux. This register is valid for H.264
and VC1 decoders only.
0 = Enable demux so that MFC generates the
descriptor information.
1 = Disable demux so that host generates the
descriptor information.
[14] Flushing DPB to discard all the output buffers in DPB
0 = Normal operation
1 = Flushing DPB
[13:0] Number of DPB that host prepared for decoding
Description
Description
6 5BMULTI FORMAT CODEC
Initial State
0
Initial State
0
0
0
0
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