Samsung S5PC110 Manual page 1707

S5PC110_UM
10.3.5.19 Interrupt Control Register (I2S_IRQ_MASK, R/W, Address = 0xFA14_005C)
I2S_IRQ_MASK
-
int_2_mask
-
10.3.5.20 Interrupt Control Register (I2S_IRQ_STATUS, R/W, Address = 0xFA14_0060)
I2S_IRQ_STATUS
-
int_2
-
For bit[1], the following holds:
Reading returns the interrupt request status.
0: Has no effect.
Warning:
1: Clears the interrupt request.
Bit
[7:2] Reserved
[1] Disables interrupt request by int_2 interrupt.
0 = Disables int_2 interrupt
1 = Enables int_2 interrupt
[0] Reserved
Bit
[7:2] Reserved
[1] Specifies the interrupt status, that is, the wrong register
setting.
This interrupt is asserted if the I2S_CON_2.bit_ch is set
to 32fs, while I2S_CON_2.data_num is set to either 20-bit
or 24-bit.
According to the wrong register setting, some audio data
MSB bits may be removed. The audio data is not
available.
[0] Reserved
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Description
Initial State
6b000000
0
0
Initial State
0
0
0
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