Samsung S5PC110 Manual page 2026

S5PC110_UM
Table 1-11 Memory Port 1, 2 Interface Timing Constants (LPDDR1 SDRAM)
(VDDINT = 1.1V ± 5%, TA = -25 to 85°C, VDDm1 = 1.7V – 1.9V)
DDR SDRAM Address Delay
DDR SDRAM Chip Select Delay
DDR SDRAM Row active Delay
DDR SDRAM Column active Delay
DDR SDRAM Write enable Delay
DDR SDRAM Output data access time from CK
DDR SDRAM Row Precharge time
DDR SDRAM RAS to CAS delay
DDR SDRAM Write recovery time
DDR SDRAM Clock low level width
DDR SDRAM Read Preamble
DDR SDRAM Read Postamble
DDR SDRAM Write Postamble time
DDR SDRAM Clock to valid DQS-In
DDR SDRAM DQS-In Setup time
DDR SDRAM DQS-In Hold time
DDR SDRAM DQS-In high level width
DDR SDRAM DQS-In low level width
DDR SDRAM read Data Setup time
Load Capacitance
Parameter
Xm1*, Xm2
Symbol Minimum
t
2.48
SAD
t
2.62
SCSD
t
2.63
SRD
t
2.62
SCD
t 2.62
SWD
t
2.00
SAC
t
18.00
RP
t
18.00
RCD
t
12.00
WR
t
0.45
CL
t
0.90
RPRE
t 0.40
RPST
t
0.40
WPST
t
0.75
DQSS
t
1.30
WPRES
t
1.30
WPREH
t
0.35
DQSH
t
0.35
DQSL
t -
DDS
< 15pF
1 ELECTRICAL DATA
Maximum Unit
3.51 ns
3.72 ns
3.73 ns
3.72 ns
3.73 ns
5.50 ns
- ns
- ns
- ns
0.55 tCK
1.10 tCK
0.60 tCK
0.60 tCK
1.25 tCK
- ns
- ns
0.60 tCK
0.60 tCK
0.50 ns
1-19