Samsung S5PC110 Manual page 1814

S5PC110_UM
1.6.2.3 Audio Subsystem Clock Gate Register (Audio Subsystem CLK GATE R/W, Address =
0xEEE1_0008)
AUDIO SUBSYSTEM
CLK GATE
Reserved
CLK_I2S
AUDIO_BUS_CLK_
I2S
AUDIO_BUS_CLK_
UART
AUDIO_BUS_CLK_
HWA
AUDIO_BUS_CLK_
DMA
AUDIO_BUS_CLK_
BUF
AUDIO_BUS_CLK_
RP
Bit
[31:7] Reserved
[6] Specifies the gating clock of I2SCLK to I2S
(0: mask, 1: pass).
[5] Specifies the gating AUDIO BUS CLK to I2S
(0: mask, 1: pass).
[4] Specifies the gating AUDIO BUS CLK to UART
(0: mask, 1: pass).
[3] Specifies the gating AUDIO BUS CLK to HWA
(0: mask, 1: pass).
[2] Specifies the gating AUDIO BUS CLK to DMA
(0: mask, 1: pass).
[1] Specifies the gating AUDIO BUS CLK to BUF (IBUF0, 1/
OBUF0, 1)
(0: mask, 1: pass).
[0] Specifies the gating AUDIO BUS CLK to RP (including IMEM
and DMEM)
(0: mask, 1: pass).
Description
1 AUDIO SUBSYSTEM
Initial State
0
1
1
1
1
1
1
1
1-10