Samsung S5PC110 Manual page 1917

S5PC110_UM
6.6.1.1 SPDIFOUT Clock Control Register (SPDCLKCON, R/W, Address = 0XE110_0000)
SPDCLKCON
-
Main Audio Clock Selection
SPDIFOUT clock down ready
(read only)
SPDIFOUT power on
6.6.1.2 SPDIFOUT Control Register (SPDCON, R/W, Address = 0XE110_0004)
SPDCON
-
FIFO Level
FIFO Level Threshold
FIFO transfer mode
FIFO_level Interrupt Status
FIFO_level Interrupt Enable
endian format
Bit
[31:3] Reserved
[2] 0 = Internal clock (I_MCLK_INT)
1 = External clock (I_MCLK_EXT)
[1] 0 = Clock-down not ready
1 = Clock-down ready
[0] 0 = Power off
1 = Power on
Bit
[31:27] Reserved
[26:22] FIFO Level Monitoring (Read Only)
FIFO depth is 16
*0 = Empty of FIFO Level, 16 = Full of FIFO Level
[21:19] FIFO Threshold Level is controllable
000 = 0-FIFO Level
001 = 1-FIFO Level
010 = 4-FIFO Level
011 = 6-FIFO Level
100 = 10-FIFO Level
101 = 12-FIFO Level
110 = 14-FIFO Level
111 = 15-FIFO Level
[18:17] 00 = DMA transfer mode
01 = Polling mode
10 = Interrupt mode
11 = Reserved
[16] Read Operation
0 = No interrupt pending.
1 = Interrupt pending.
Write Operation
0 = No effect.
1 = Clear this flag.
[15] 0 = Interrupt masked
1 = Interrupt enable
[14:13] 00 = big endian
o_data = {in_data[23:0]}
01 = 4 byte swap
o_data={in_data[15:8], in_data[23:16],
in_data[31:24]}
Description
Description
6 SPDIF TRANSMITTER
Initial State
0
0
1
0
Initial State
0
00000
000
00
0
0
0
6-11