Samsung S5PC110 Manual page 1990

Risc microprocessor
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S5PC110_UM
2.3.2.5 HASH and PRNG Control (HASH_BYTE_SWAP, R/W, Address = 0xEA00_600C)
HASH_BYTE_
SWAP
HASH_SWAP_DI
HASH_SWAP_DO
HASH_SWAP_IV
NOTE:
1.
If HASH_SWAP_DI or HASH_SWAP_IV is 0, data will enter the hash core in the same order as HWDATA [31:0].
Otherwise, the 32-bit word is byte-swapped before entering the hash core. Note that the hash core is designed with
"big endian" in mind, so you should turn on byte swapping if the bus is little endian.
2.
SHA1(abcd) = 81fe8bfe_87576c3e_cb22426f_8e578473_82917acf
READ(HASH_RESULT_1)
READ(HASH_RESULT_1)
MD5(abcd) = e2fc714c_4727ee93_95f324cd_2e7f331f
READ(HASH_RESULT_1)
READ(HASH_RESULT_1)
3.
You must correctly configure the byte swapping before starting a hash/HMAC operation. (This step is omitted in the
example code for simplicity.)
Bit
[3]
Specifies the Byte swap of data input.
0 = Does not swap (default)
1 = Swap
[2]
Specifies the Byte swap of data output (hash result).
0 = Does not swap (default)
1 = Swap
[1]
Specifies the Byte swap of custom IVs.
0 = Does not swap (default)
1 = Swap
HRDATA = 0x81fe8bfe (when HASH_SWAP_DO = 0)
HRDATA = 0xfe8bfe81 (when HASH_SWAP_DO = 1)
HRDATA = 0xe2fc714c (when HASH_SWAP_DO = 0)
HRDATA = 0x4c71fce2 (when HASH_SWAP_DO = 1)
Description
2 ADVANCED CRYPTO ENGINE
R/W
Initial State
0
0
0
2-35

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