Samsung S5PC110 Manual page 1719

S5PC110_UM
10.3.6.41 HDCP E-FUSE Control Register (EFUSE_FSET_DE-ASSERT, R/W, Address = 0xFA16_0020)
EFUSE_FSET_DEASSERT
EFUSE_FSET_DEASSERT
10.3.6.42 HDCP E-FUSE Control Register (EFUSE_SENSING, R/W, Address = 0xFA16_0024)
EFUSE_SENSING
EFUSE_SENSING
10.3.6.43 HDCP E-FUSE Control Register (EFUSE_SCK_ASSERT, R/W, Address = 0xFA16_0028)
EFUSE_SCK_ASSERT
EFUSE_SCK_ASSERT
10.3.6.44 HDCP E-FUSE Control Register (EFUSE_SCK_DEASSERT, R/W, Address = 0xFA16_002C)
EFUSE_SCK_DEASSERT
EFUSE_SCK_DEASSERT
10.3.6.45 HDCP E-FUSE Control Register (EFUSE_SDOUT_OFFSET, R/W, Address = 0xFA16_0030)
EFUSE_SDOUT_OFFSET
EFUSE_SDOUT_OFFSET
10.3.6.46 HDCP E-FUSE Control Register (EFUSE_READ_OFFSET, R/W, Address = 0xFA16_0034)
EFUSE_READ_OFFSET
EFUSE_READ_OFFSET
Bit
[7:0] Specifies the FSET de-asserting position
(Unit: HDMI link PCLK, default: 83MHz, 12n)
Bit
[7:0] Specifies the sensing width
(Unit: HDMI link PCLK, default: 83MHz, 12n).
Bit
[7:0] Specifies the SCK asserting position
(Unit: HDMI link PCLK, default: 83MHz, 12n)
Bit
[7:0] Specifies the SCK de-asserting position
(Unit: HDMI link PCLK, default: 83MHz, 12n)
Bit
[7:0] Specifies the SDOUT offset
(Unit: HDMI link PCLK, default: 83MHz, 12n)
Bit
[7:0] Specifies the READ Offset
(Unit: HDMI link PCLK, default: 83MHz, 12n).
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Description
Description
Description
Description
Description
Initial State
0x10
Initial State
0x14
Initial State
0x4
Initial State
0xC
Initial State
0x10
Initial State
0x14
10-110