Samsung S5PC110 Manual page 1835

S5PC110_UM
The Data is aligned in the RX FIFO for 24-bit/channel BLC as shown in
31
INVALID
INVALID
INVALID
INVALID
The RXCHPAUSE in the I2SCON register can stop the serial data reception on the I2SSDI. The reception is
stopped once the current Left/Right channel is received.
If the control registers in the I2SCON Register (IIS Control Register) and I2SMOD Register (IIS Mode
Register) are to be reprogrammed then it is advisable to disable the RX channel.
The Status of RX FIFO can be checked by checking the bits in the I2SFIC Register (IIS FIFO Control Register).
BLC = 10 (24-bit/channel)
23
Figure 2-10 RX FIF0 Structure for BLC = 10 (24-bit/channel)
Figure 2-10.
Left Channel
Right Channel
Left Channel
Right Channel
2 IIS MULTI AUDIO INTERFACE
0
LOC 0
LOC 1
LOC 2
LOC 3
LOC 4
LOC 5
LOC 6
LOC 7
LOC 8
LOC 9
LOC 10
LOC 11
LOC 12
LOC 13
LOC 14
LOC 15
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