Samsung S5PC110 Manual page 1975

S5PC110_UM
2.3.1.12 Feed Control (FCBTDMAC, R/W, Address = 0xEA00_0038)
FCBTDMAC
Reserved
BYTESWAP
FLUSH
2.3.1.13 Feed Control (FCHRDMAS, R/W, Address = 0xEA00_0040)
FCHRDMAS
STARTADDR
2.3.1.14 Feed Control (FCHRDMAL, R/W, Address = 0xEA00_0044)
FCHRDMAL
LENGTH
Bit
[31:2] Reserved
[1] If this bit is high, then the data written to the bus is byte-
swapped in a word boundary. If this bit is low (default),
then the data is handed over to the FIFO without byte-
swap. For little endian bus, this bit should be '1'.
[0] If this bit is high, then data flushes out from FIFO and
DMA. After flushing, the start address keeps the
stopped address, and the length is 0. The flushing state
should be released by writing value '0' to this bit.
Bit
[31:0] Specifies the Start Address of DMA. The address does
not to be aligned by 32-bit. Its value increases by 4 after
every transaction.
Bit
[31:0] Specifies the Block length of DMA. The length needs
not to be aligned by 32-bit. Its value decreases by 4
after every transaction.
Description
Description
Description
2 ADVANCED CRYPTO ENGINE
R/W Initial State
0
0
0
R/W Initial State
0
R/W Initial State
0
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