Samsung S5PC110 Manual page 1499

S5PC110_UM
7.12.1.1 SDO Clock Control Register (SDO_CLKCON, R/W, Address = 0xF900_0000)
SDO_CLKCON
Reserved
SDO software reset
Reserved
SDO clock down ready
(read only)
SDO clock on
Image Mixer transmits video data to TVENC. To connect Image Mixer and TVENC you must configure
REG_DST_SEL at mixer_CFG register (0xF920_ 0004. To synchronous between Image Mixer and TVENC you
must configure Image Mixer I/F clock (VCLKHS) and VCLKS (TVENC clock) (fixed by 54MHz). Thus, you must set
MIXER_SEL register in CLK_SRC1(0xE010_0204). For more information, refer to CMU chapter.
Bit
[31:5] Reserved, read as zero, do not modify
[4] This bit controls software reset of TVOUT.
Software reset is active high signal.
0 = No reset
1 = Enables software reset
[3:2] Reserved, read as zero, do not modify
[1] Indicates whether host controller can stop the clock for
the TVOUT.
0 = Clock-down not ready
1 = Clock-down ready
Normally this bit is 0. After SDO_CLKCON [0] bit is 0, if
the internal line counter and pixel counter are 0 (just
before starting line 1), this bit will be 1.
[0] This bit determines run/ stop mode of TVOUT.
0 = TVOUT clock off. TVOUT requests for clock down to
host controller. If SDO is ready for clock down,
SDO_CLKCON [1] bit will be 1. The host controller
should stop the clock for the TVOUT after that.
1 = TVOUT clock on. TVOUT starts running.
NOTE: Vertical Sync of TVENC's Timing Generator
updates the SFRs of Video Processor and Image Mixer.
Thus, SFRs are configured before this bit is enabled.
The sequence to enable TVSS is as follows: "VP ->
MIXER -> TVENC".
Also, because of the same reason, the disabling
sequence is following as : "VP -> MIXER -> TVNEC".
Description
7 6BTVOUT & VIDEO DAC
Reset Value
0
0
0
0
7-27