Samsung S5PC110 Manual page 1445

S5PC110_UM
6.3.3.4.10 Current C Address Register (MFC_COMMON_CHx_RG_5, R/W, Address = 0xF170_2054 or
0xF170_2094)
MFC_COMMON_CHx
_RG_5
CURRENT_C_ADDR
NOTE: The address should be in Port_B (i.e., the address should be between MC_DRAMBASE_ADDR_B and
MC_DRAMBASE_ADDR_B+256MB).
The buffer address should be aligned as follows.
- Tile mode : align(align(x_size, 128) * y_size/2, 8192)
- Linear mode : align(align(x_size, 16) * y_size/2, 2048)
6.3.3.4.11 Frame Insertion Control Register (MFC_COMMON_CHx_RG_6, R/W, Address = 0xF170_2058 or
0xF170_2098)
MFC_COMMON_CHx
_RG_6
RESERVED
NOT_CODED
I_FRAME
6.3.3.4.12 Auxiliary Host Command Register (MFC_COMMON_CHx_RG_9, R/W, Address = 0xF170_2064 or
0xF170_20A4)
MFC_COMMON_CHx
_RG_9
HOST_WR_ADR
6.3.3.4.13 Encoder Input Buffer Flush Register (MFC_COMMON_CHx_RG_10, R/W, Address =
0xF170_2068 or 0xF170_20A8)
MFC_COMMON_CHx
_RG_10
RESERVED
INPUT_BUFFER_FLU
SH
RESERVED
Bit
[31:0] The address of the current chrominance picture to encode
Bit
[31:0] Reserved
[1] Current frame must be encoded into a not coded frame
[0] Current frame must be encoded into an I frame. It will be
effective at the next anchor frame.
Bit
[31:0] The address points to a space of shared memory consisting
of multiple commands which host can read/write. The
detailed structure of the shared memory is described in
chapter 6.4
Bit
[31:15] Reserved
[14] Flushing input buffer to discard all frame in the input buffer.
0 = Normal operation
1 = Flushing input buffer
[13:0] Reserved
Description
Description
Description
Description
6 5BMULTI FORMAT CODEC
Initial State
0
Initial State
0
0
0
Initial State
0
Initial State
0
0
0
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