Samsung S5PC110 Manual page 1841

S5PC110_UM
2.9.1.2 IIS Interface Mode Register (IISMOD, R/W, Address = 0xEEE3_0004)
IISMOD
OP_CLK [31:30]
Reserved
OP_MUX_SEL
BLC_S [27:26]
BLC_P [25:24]
Reserved [23:22]
CDD2 [21:20]
CDD1 [19:18]
DCE [17:16]
Reserved
Bit
Operation clock for IIS logic.
00 = Codec clock out
01 = Codec clock in
10 = Bit clock out
11 = Audio bus clock
[29] -
[28] Mux selection for secondary TX FIFO_S
0 = TX FIFO_S gets data from APB SFR interface
1 = TX FIFO_S gets data form internal DMA interface
Before trying to change this field from 1 to 0, s/w must poll
IISTRNCNT register to confirm that all the transfer is done
according to internal DMA setting.
There is no restriction on switching from 0 to 1.
Bit Length Control Bit which decides transmission of
8/16/24 bits per audio channel for Secondary TX FIFO_S
00 = 16 Bits per channel
01 = 8 Bits Per Channel
10 = 24 Bits Per Channel
11 = Reserved
Bit Length Control Bit Which decides transmission of
8/16/24 bits per audio channel for Primary TX FIFOx
00 = 16 Bits per channel
01 = 8 Bits Per Channel
10 = 24 Bits Per Channel
11 = Reserved
-
Channel-2 Data Discard. Discard means zero padding. It
only supports 8/16 bit mode.
00 = No Discard
01 = I2STXD[15:0] Discard
10 = I2STXD[31:16] Discard
11 = Reserved
Channel-1 Data Discard. Discard means zero padding. It
only supports 8/16 bit mode.
00 = No Discard
01 = I2STXD[15:0] Discard
10 = I2STXD[31:16] Discard
11 = Reserved
Enables Data Channel.
[17]: Enables SD2 channel
[16]: Enables SD1 channel
[15] -
Description
2 IIS MULTI AUDIO INTERFACE
R/W Initial State
R/W 00
R 0
R/W 0
R/W 00
R/W 00
R 00
R/W 00
R/W 00
R/W 00
R 0
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