Samsung S5PC110 Manual page 1838

S5PC110_UM
2.9.1.1 IIS Interface Control Register (IISCON, R/W, Address = 0xEEE3_0000)
IISCON
SW_RST
Reserved [30:27]
FRXOFSTATUS
FRXOFINTEN
FTXSUR
STATUS
FTXSURINTEN
FTXSEMPT
FTXSFULL
TXSDMAPAUSE
Reserved
TXSDMACTIVE
Bit
[31] IIS s/w reset control. This should be set to 1 after IIS clock
is stable.
0 = Reset IIS module (default)
1 = Un-reset IIS module
Before reading SFR of IIS, user must set this bit.
-
[26] RX FIFO Over Flow Interrupt Status. And this is used by
interrupt clear bit. When this is high, you can do interrupt
clear by writing '1'.
0 = Interrupt does not occur.
1 = Interrupt occurs
[25] Enables RX FIFO Overflow Interrupt
0 = Disables RXFIFO Overflow INT
1 = Enables RXFIFO Overflow INT
[24] Secondary TX FIFO_S under-run interrupt status. This is
used by interrupt clear bit. When this is high, you can clear
interrupt clear by writing '1'.
0 = Interrupt does not occur.
1 = Interrupt occurs.
[23] Secondary TX FIFO_S Under-run Interrupt Enable
0 = TXFIFO_S Under-run INT disable
1 = TXFIFO_S Under-run INT enable
[22] Secondary TX FIFO_S empty Status Indication
0 = TX FIFO_S is not empty(Ready to transmit Data)
1 = TX FIFO_S is empty (Not Ready to transmit Data)
[21] Secondary TX FIFO_S full Status Indication
0 = TX FIFO_S is not full
1 = TX FIFO_S is full
[20] Tx External DMA operation for secondary TX FIFIO_S
pause command. Note that when this bit is activated, the
External DMA request will be halted after current on-going
External DMA transfer is completed.
0 = No pause External DMA operation for TX FIFO_S
1 = Pause External DMA operation for TX FIFO_S
Note: IISDMAEN SFR performs Internal DMA stop control.
[19] Reserved. This value must be 0.
[18] Tx External DMA active for secondary TX FIFO_S (start
External DMA request). Note that when this bit is set from
high to low, the External DMA operation will be forced to
stop immediately.
0 = Inactive
1 = Active
Description
2 IIS MULTI AUDIO INTERFACE
R/W Initial State
R/W 0
R 0x0
R/W 0
R/W 0
R/W 0
R/W 0
R 0
R 0
R/W 0
R/W 0
R/W 0
2-21