Samsung S5PC110 Manual page 1505

S5PC110_UM
7.12.1.9 SDO Status Register (SDO_FINFO, R, Address = 0xF900_0040)
SDO_FINFO
Reserved
Field Counter Modulo 1001
Reserved
Field ID
Field ID with Progressive/
Interlaced Indication
Bit
[31:26] Reserved, read as zero, do not modify
[25:16] This counter is used for 59.94/60.0 Hz field rate
conversion.
[15:2] Reserved, read as zero, do not modify
[1] 0 = Top field
1 = Bottom field
[0] If the SDO_CONFIG register is set to interlaced,
0 = Top field
1 = Bottom field.
If the SDO_CONFIG register is set to progressive,
this bit would be fixed to zero
Description
7 6BTVOUT & VIDEO DAC
Initial State
0
0
0
1
0
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