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S5PC110_UM
•
JTAG (Dedicated)
Ball Name
XJTRSTN
XJTMS
XJTCK
XJTDI
XJTDO
XJDBGSEL
•
RESET / etc (Dedicated)
Ball Name
XOM_0 ~ XOM_5
XDDR2SEL
XPWRRGTON
XNRESET
XCLKOUT
XNRSTOUT
XNWRESET
XRTCCLKO
I/O
XjTRSTn (TAP Controller Reset) resets the TAP controller at start.
I
If debugger(black ICE) is not used, XjTRSTn pin must be at L or low active pulse.
Pull-down resistor is connected.
XjTMS (TAP Controller Mode Select) controls the sequence of the TAP
I
controller's states.
Pull-up resistor is connected.
XjTCK (TAP Controller Clock) provides the clock input for the JTAG logic.
I
Pull-down resistor is connected.
XjTDI (TAP Controller Data Input) is the serial input for test instructions and data.
I
Pull-up resistor is connected.
XjTDO (TAP Controller Data Output) is the serial output for test instructions and
O
data.
I
JTAG selection. 0: CORTEXA8 Core JTAG, 1: Peripherals JTAG
I/O
I
Operating Mode control signals (6bit)
I
Selection DDR type (LPDDR1/2 or DDR2). 0: LPDDR1/2, 1: DDR2
O
Power Regulator enable
I
System Reset
O
Clock out signal
I
For External device reset control
I
System Warm Reset.
O
RTC Clock out
5 G TYPE SIZE & BALL MAP
Description
Description
5-35
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