Samsung S5PC110 Manual page 1440

S5PC110_UM
6.3.3.3.16 DivX311 Horizontal Resolution Register (MFC_COMMON_CHx_RG_5, W, Address =
0xF170_2054 or 0xF170_2094)
MFC_COMMON_CHx_
RG_5
DIVX311_HRESOL
6.3.3.3.17 CPB Size Register (MFC_COMMON_CHx_RG_6, R/W, Address = 0xF170_2058 or 0xF170_ 2098)
MFC_COMMON_CHx_
RG_6
CPB_SIZE
NOTE: CPB_SIZE = align(CH_ES_DEC_UNIT_SIZE+64, pow(2KB)) for H.264 and VC1 decoders when DMX is enabled,
where pow(2KB)=1KB, 2KB, 4KB, 8KB, ..., 4MB.
6.3.3.3.18 Descriptor Buffer Size Register (MFC_COMMON_CHx_RG_7, R/W, Address = 0xF170_205C or
0xF170_209C)
MFC_COMMON_CHx_
RG_7
DESC_SIZE
6.3.3.3.19 Release Buffer Register (MFC_COMMON_CHx_RG_8, R/W, Address = 0xF170_2060 or
0xF170_20A0)
MFC_COMMON_CHx_
RG_8
RELEASE_BUFFER
Bit
[31:0] Horizontal resolution of the current channel. It should be
set before frame decoding.
Bit
[31:0] CPB size register should be set before SEQ_START and
FRAME_START. The maximum CPB size is 4MB.
Bit
[31:0] Descriptor buffer size register should be set before
SEQ_START and FRAME_START.
The maximum descriptor buffer size is 128KB.
Bit
[31:0] Release buffer register specifies the availability of each
DPB.
The nth bit specifies the availability of the nth DPB.
1 means free and 0 means busy.
Description
Description
Description
Description
6 5BMULTI FORMAT CODEC
Initial State
0
Initial State
0
Initial State
0
Initial State
0
6-48