Samsung S5PC110 Manual page 1848

S5PC110_UM
IISAHB Bit
IISDMAEN [0]
2.9.1.10 IIS AHB DMA Start Address0 Register (IISSTR0, R/W, Address = 0xEEE3_0024)
IISSTR0 Bit
IISSTR [31:0]
2.9.1.11 IIS AHB DMA Start Address1 Register (IISSTR1, R/W, Address = 0xEEE3_0040)
IISSTR1 Bit
IISSTR1 [31:0]
Enable IIS internal DMA
Users can use internal DMA in IIS after this bit field is ON.
Internal DMA can issue 32-bit single read transaction for AHB
and TXFIFO0 will hold data returned by DMA.
Warning>
If IISDMARLD is set, IISDMAEN bit will be automatically
cleared when reload operation is in progress. After auto-
reload operation is done, IISDMAEN bit will be automatically
set.
When auto-reload operation is in progress, s/w intervention
on this field will cause mal-function of internal DMA
operations. To manipulate IISAHB register, s/w must check
that IISDMAEN is in stable state.
Start address0 of IIS internal DMA operation.
When DMAEN is ON, internal DMA in IIS will start DMA
operation based on IISSTR0 address.
Internal DMA can handle word-aligned address only but to get
best performance, IISSTR0 should be 64 word-aligned
address.
Start address1 of IIS internal DMA operation.
When DMAEN is ON, internal DMA in IIS will start DMA
operation based on IISSTR1 address.
Internal DMA can handle word-aligned address only, but to
achieve best performance, IISSTR1 should be 64 word-
aligned address.
Description
Description
Description
2 IIS MULTI AUDIO INTERFACE
R/W Initial State
R/W 0
R/W Initial State
R/W 0x00
R/W Initial State
R/W 0x00
2-31