Samsung S5PC110 Manual page 1642

S5PC110_UM
10.3.2.5 Control Register (AUDIO_CLKSEL, R/W, Address = 0xFA10_0010)
AUDIO_CLKSEL
-
AUDIO_CLK
10.3.2.6 Control Register (HDMI_PHY_RSTOUT, R/W, Address = 0xFA10_0014)
PHY_RSTOUT
-
RSTOUT
10.3.2.7 Control Register (HDMI_PHY_VPLL, R, Address = 0xFA10_0018)
PHY_VPLL
VPLL_LOCK
-
VPLL_CODE
Bit
[7:1] Reserved
[0] Specifies the clock selection of Audio system (Must be
higher than 512*fs).
0 = PCLK
1 = SPDIF clock
Note: For audio data capture, the frequency of audio
clock is higher than 512*fs[Hz]. If the frequency of audio
clock is less than 512fs[Hz], audio data may be missed.
Thus, if the frequency of PCLK is below 512fs[Hz], select
SPDIF clock after it makes the frequency of SPDIF clock
be higher than 512fs[Hz].
Bit
[7:1] Reserved
[0] Specifies the HDMI PHY Software Reset out (active
high).
0 = Normal
1 = Reset
Bit
[7] Specifies the HDMI PHY VPLL Locking.
[6:4] Reserved
[3:0] Specifies the HDMI PHY VPLL Code.
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Description
Description
Initial State
0x00
0
Initial State
0x00
0
Initial State
0x0
0x0
0x0
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