Samsung S5PC110 Manual page 1881

S5PC110_UM
4.3.6 AC97 POWER-DOWN
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
4.3.6.1 Powering Down the AC-link
The AC-link signals enter a low power mode when the AC97 Codec Power-down register (0x26) bit PR4 is set to 1
(by writing 0x1000). Then the Primary Codec drives both BITCLK and SDATA_IN to a logic low voltage level. The
sequence follows the timing diagram as shown in
The AC97 Controller transmits the write to Power-down register (0x26) via AC-link. Set up the AC97 Controller so
that it does not transmit data to slots 3-12 when it writes to the Power-down register bit PR4 (data 0x1000), and it
does not require the Codec to process other data when it receives a power down request. When the Codec
processes the request it immediately transitions BITCLK and SDATA_IN to a logic low level. The AC97 Controller
drives SYNC and SDATA_OUT to a logic low level after programming the AC_GLBCTRL register.
slot 12
TAG
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slot 12
TAG
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Figure 4-7 AC97 Power-down Timing
Figure 4-7.
Write to Data
0X26 PR4
4 AC97 CONTROLLER
4-9