Samsung S5PC110 Manual page 1816

S5PC110_UM
1.6.3.6 RP Boot Register (RP_BOOT, R/W, Address = 0xEEE2_012C)
RP_BOOT
SW_DEFINE
RP boot
At ARM decode mode, RP boot bit must be 1.
1.6.3.7 PAD Power Down Control Register (PAD_PDN_CTRL, R/W, Address = 0xEEE2_0204)
GPIO PDN controls power down. The value of each PAD set by this SFR is maintained at Sleep power mode.
PAD_PDN_CTRL
Reserved
SDO_PDN[2]
SDO_PDN[1]
SDO_PDN[0]
SCLKO_PDN
CDCLKO_PDN
LRCLKO_PDN
SCLKO_EN_PDN
CDCLKO_EN_PDN
LRCLKO_EN_PDN
Bit
[31:1] Specifies an SFR that can be freely used in the application.
[0] 1 = Internal (Instruction is located in IMEM)
0 = External (Instruction is located in DRAM and start
address is defined at INST_START_ADDR SFR)
Bit
[31:9] Reserved
[8] Configure output value of I2S0 SDO[2] PAD
0 = Output 0
1 = Output 1
[7] Configure output value of I2S0 SDO[1] PAD
0 = Output 0
1 = Output 1
[6] Configure output value of I2S0 SDO[0] PAD
0 = Output 0
1 = Output 1
[5] Configure output value of I2S0 SCLK PAD
0 = Output 0
1 = Output 1
[4] Configure output value of I2S0 CDCLK PAD
0 = Output 0
1 = Output 1
[3] Configure output value of I2S0 LRCLK PAD
0 = Output 0
1 = Output 1
[2] Configure direction of I2S0 SLCK PAD
0 = Input
1 = Output
[1] Configure direction of I2S0 CDCLK PAD
0 = Input
1 = Output
[0] Configure direction of I2S0 LRCLK PAD
0 = Input
1 = Output
Description
Description
1 AUDIO SUBSYSTEM
Initial State
0
0
Initial State
0
0
0
0
0
0
0
0
0
0
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