Samsung S5PC110 Manual page 1977

S5PC110_UM
2.3.1.18 Feed Control (FCPKDMAC, R/W, Address = 0xEA00_0058)
FCPKDMAC
Reserved
BYTESWAP
DESCEND
TRANSMIT
FLUSH
2.3.1.19 Feed Control (FCPKDMAO, R/W, Address = 0xEA00_005C)
FCPKDMAO
Reserved
SRAMOFFSET
Bit
[31:4] Reserved
[3] If this bit is high, then the data read from or written to
the bus is byte-swapped in a word boundary. If this bit is
low (default), then the data is handed over to the FIFO
without byte-swap.
[2] If this bit is low (default), then offset value in
FCPKDMAO increases by 4 after every transfer. If this
bit is high, then offset value in FCPKDMAO decreases
by 4 after every transfer.
[1] Selects receiving (0) or transmitting (1).
[0] If this bit is high, then data flushes out from FIFO and
DMA. After flushing, the start address keeps the
stopped address, and the length is 0. The flushing state
should be released by writing value '0' to this bit.
Bit
[31:12] Reserved
[11:0] Specifies the Address offset in PKA SRAM. The
address needs to be aligned by 32-bit. Its value
increases by 4 after every transfer (decreases by 4, if
DESCEND in FCPKDMAC is high).
Description
Description
2 ADVANCED CRYPTO ENGINE
R/W Initial State
0
0
0
0
0
R/W Initial State
0
0
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