Samsung S5PC110 Manual page 1822

S5PC110_UM
and
Figure 2-4 Table 2-1
1) Slave mode
ASS_CLK_CON
Don ' t care
XXTI
2) Master mode (EPLL out)
ASS_CLK_CON
EPLL/2
EPLL
3) Master mode (External Clock in)
ASS_CLK_CON
IISCDCLK0
EPLL
Mode
Slave mode
Master mode
(EPLL out)
Master mode
(External clock in)
shows typical usage example of Master EPLL out, Master External clock and Slave.
I2S V5.1 controller
x
I2SCLK
RCLKSRC
AudioBusCLK
OP_CLK
I2S V5.1 controller
I2SCLK
RCLKSRC
AudioBusCLK
OP_CLK
I2S V5.1controller
I2SCLK
RCLKSRC
AudioBusCLK
OP_CLK
Figure 2-4
Table 2-1 Typical Usage of Master/Slave Modes
AudioSS CLK_CON
AudioBusClk I2SCLK
XXTI or EPLL Gating
EPLL EPLL/2
EPLL IISCDCLK0
x
CDCLK
(IN)
SCLK/
LRCLK
slave
CDCLK
(OUT)
SCLK/
LRCLK
master
External clock
CDCLK
(IN)
SCLK/
LRCLK
master
Master/Slave Modes of IIS
MSS RCLKSRC
1 1
(Slave) (I2SCLK)
0 1
(Master) (I2SCLK)
0 1
(Master) (I2SCLK)
2 IIS MULTI AUDIO INTERFACE
Codec chip
SCLK/
LRCLK
master
Codec chip
SCLK/
LRCLK
slave
Codec chip
SCLK/
LRCLK
slave
IIS v5.1 IISMOD
OP_CLK
3
(AudioBusClk)
3
(AudioBusClk)
3
(AudioBusClk)
CDCLKCON
1
(In)
0
(Out)
1
(In)
2-5