Samsung S5PC110 Manual page 1877

S5PC110_UM
4.3.4 AC-LINK DIGITAL INTERFACE PROTOCOL
Each AC97 Codec incorporates a five-pin digital serial interface that links it to the S5PC110 AC97 Controller. AC-
link is a full-duplex, fixed-clock and PCM digital stream. It employs a time division multiplexed (TDM) scheme to
handle control register accesses and multiple input and output audio streams. The AC-link architecture divides
each audio frame into 12 outgoing and 12 incoming data streams. Each stream has 20-bit sample resolution and
requires a DAC and an analog-to-digital converter (ADC) with a minimum 16-bit resolution.
Slot #
0
SYNC TAG
Phase
SDATA_OUT
TAG
SDATA _IN
TAG
shows the slot definitions supported by S5PC110 AC97 Controller. The S5PC110 AC97 Controller
Figure 4-4
provides synchronization for all data transaction on the AC-link.
A data transaction is made up of 256 bits of information broken into groups of 13 time slots and is called a frame.
Time slot 0 is called the Tag Phase and it is 16 bits long. The other 12 time slots are called the Data Phase. The
Tag Phase contains one bit that identifies a valid frame and 12 bits that identify the time slots in the Data Phase
that contain valid data. Each time slot in the Data Phase is 20 bits long. A frame begins when SYNC goes high.
The amount of time that SYNC is high corresponds to the Tag Phase. AC97 frames occur at fixed 48 kHz intervals
and are synchronous to the 12.288 MHz bit rate clock, BITCLK.
The controller and the Codec use the SYNC and BITCLK to determine when to send transmit data and when to
sample received data. A transmitter transitions the serial data stream on each rising edge of BITCLK and a
receiver samples the serial data stream on falling edges of BITCLK. The transmitter must tag the valid slots in its
serial data stream. The valid slots are tagged in slot 0. Serial data on the AC-link is ordered most significant bit
(MSB) to least significant bit (LSB). The Tag Phase's first bit is bit 15 and the first bit of each slot in Data Phase is
bit 19. The last bit in any slot is bit 0.
1 2 3
CMD CMD PCM
ADDR DATA LEFT RIGHT
STATUS STATUS PCM
ADDR DATA LEFT RIGHT
Figure 4-4 Bi-directional AC-link Frame with Slot Assignments
4 5 6
Data
Phase
PCM
RSRVD RSRVD RSRVD
PCM
PCM
RSRVD RSRVD
MIC
7 8 9 10
RSRVD RSRVD RSRVD
RSRVD RSRVD RSRVD
4 AC97 CONTROLLER
11 12
RSRVD RSRVD
RSRVD RSRVD
4-5