Samsung S5PC110 Manual page 1695

S5PC110_UM
10.3.4.16 SPDIFIN Info Register (SPDIFIN_CH_STATUS_1, R, Address = 0xFA13_0048)
SPDIFIN_CH_STATUS_1
frame_cnt_low
10.3.4.17 SPDIFIN Info Register (SPDIFIN_CH_STATUS_2, R, Address = 0xFA13_004C)
SPDIFIN_CH_STATUS_2
frame_cnt_high
Bit
[7:0] Specifies the frame count value [7:0].
Frame_cnt register has 16-bits value. This is low by 8-
bits.
The period of a frame (two sub-frames) and register is
updated every two sub-frames.
It will be measured by 'SPDIFIN_internal_clk' made with
SPDIFIN_CONFIG.clk_divisor.
Unit: SPDIF_internal_clk cycles
Recommended value for locking incoming signals: Over
0x220 (8.5timesx64-bits)
Bit
[7:0] Specifies the frame count value [15:8].
Frame_cnt register has 16-bits value. This is high by 8-
bits.
The period of a frame (two sub-frames) and register is
updated every two sub-frames. It is measured by
'SPDIFIN_internal_clk' made with
SPDIFIN_CONFIG.clk_divisor.
Unit: SPDIF_internal_clk cycles
Recommended value for locking incoming signals: Over
0x220 (8.5timesx64-bits)
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Description
Initial State
0x00
Initial State
0x0
10-86