Samsung S5PC110 Manual page 1439

Risc microprocessor
Table of Contents

Advertisement

S5PC110_UM
6.3.3.3.12 CH External Stream Buffer Address Register (MFC_COMMON_CHx_RG_1, R/W, Address =
0xF170_2044 or 0xF170_2084)
MFC_COMMON_CHx_
RG_1
CH_ES_ADDR
NOTE: The address should be in Port_A (i.e., the address should be between MC_DRAMBASE_ADDR_A and
MC_DRAMBASE_ADDR_A+256MB).
6.3.3.3.13 CH Decoding Unit Size Register (MFC_COMMON_CHx_RG_2, R/W, Address = 0xF170_2048 or
0xF170_2088)
MFC_COMMON_CHx_
RG_2
CH_ES_DEC_UNIT_
SIZE
6.3.3.3.14 CH Descriptor Buffer Address (MFC_COMMON_CHx_RG_3, R/W, Address = 0xF170_204C or
0xF170_208C)
MFC_COMMON_CHx_
RG_3
CH_DESC_ADDR
NOTE: The address should be in Port_A (i.e., the address should be between MC_DRAMBASE_ADDR_A and
MC_DRAMBASE_ADDR_A+256MB).
6.3.3.3.15 DivX311 Vertical Resolution Register (MFC_COMMON_CHx_RG_4, W, Address = 0xF170_2050
or 0xF170_2090)
MFC_COMMON_CHx_
RG_4
DIVX311_VRESOL
Bit
[31:0]
Start address of the CPB of the elementary stream to be
decoded
Bit
[31:0]
Decoding unit size in the CPB
Bit
[1:0]
Channel descriptor buffer address
Bit
[31:0]
Vertical resolution of the current channel. It should be set
before frame decoding.
Since Divx 3.11 does not have header information in the
ES format, it should be informed separately.
Description
Description
Description
Description
6 5BMULTI FORMAT CODEC
Initial State
0
Initial State
0
Initial State
0
Initial State
0
6-47

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents