Samsung S5PC110 Manual page 1370

Risc microprocessor
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S5PC110_UM
4.3 INTERFACE AND PROTOCOL
Specifies the interval between rising of VVALID and first rising of
t1
HVALID.
Specifies the interval between last falling of DVALID and falling of
t2
HVALID.
Specifies the interval between falling of HVALID and rising of next
t3
HVALID.
Specifies the interval between rising of HVALID and first rising of
t4
DVALID.
Specifies the interval between last falling of HVALID and falling of
t5
VVALID.
Specifies the interval between falling of VVALID and rising of next
t6
VVALID.
Figure 4-2
Waveform of Output Data
Table 4-1
Timing Diagram of Output Data
Description
4 3BMIPI CSIS
Minimum Cycle of Pixel Clock
Vsync_SIntv + 1 (1 ~ 64)
Hsync_LIntv + 2 (2 ~ 66)
1
0
Vsync_EIntv (0 ~ 4095)
1
4-3

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