Samsung S5PC110 Manual page 2349

S5PC110_UM
Pin Name
XM0ADDR_15 EBI_ADDR[15]
XM0DATA_0 EBI_DATA[0]
XM0DATA_1 EBI_DATA[1]
XM0DATA_2 EBI_DATA[2]
XM0DATA_3 EBI_DATA[3]
XM0DATA_4 EBI_DATA[4]
XM0DATA_5 EBI_DATA[5]
XM0DATA_6 EBI_DATA[6]
XM0DATA_7 EBI_DATA[7]
XM0DATA_8 EBI_DATA[8]
XM0DATA_9 EBI_DATA[9]
XM0DATA_10 EBI_DATA[10]
XM0DATA_11 EBI_DATA[11]
XM0DATA_12 EBI_DATA[12]
XM0DATA_13 EBI_DATA[13]
XM0DATA_14 EBI_DATA[14]
XM0DATA_15 EBI_DATA[15]
Signal
SROM_CSn[5:4]
SROM_CSn[3:2]
SROM_CSn[1:0]
EBI_OEn
EBI_WEn
EBI_BEn[1:0]
SROM_WAITn
EBI_DATA_RDn
NF_CLE
NF_ALE
NF_FWEn
NF_FREn
NF_RnB[3:0]
EBI_ADDR[15:0]
EBI_DATA[15:0]
NFCSn[0]
Func0 Func1
Signal IO Signal
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I/O
O Memory Port 0 SROM Chip select support up to 2 memory bank
O Memory Port 0 SROM Chip select support up to 2 memory bank
O Memory Port 0 SROM Chip select support up to 2 memory bank
O Memory Port 0 SROM / OneNAND Output Enable
O Memory Port 0 SROM / OneNAND Write Enable
O Memory Port 0 SROM Byte Enable
I Memory Port 0 SROM nWait
O Memory Port 0 SROM/OneNAND/NAND/CF Output Enable
O Memory Port 0 NAND Command Latch Enable
O Memory Port 0 NAND Address Latch Enable
O Memory Port 0 NAND Flash Write Enable
O Memory Port 0 NAND Flash Read Enalbe
I Memory Port 0 NAND Flash Ready/Busy
O Memory port 0 Address bus
IO Memory port 0 Data bus
O Memory Port 0 NAND Chip Select bank 0
Func2
IO Signal IO
Description
6 H TYPE SIZE & BALL MAP
Func3 Default
Signal IO
Func0
Func0
Func0
Func0
Func0
Func0
Func0
Func0
Func0
Func0
Func0
Func0
Func0
Func0
Func0
Func0
Func0
Reset
O(L)
O(L)
O(L)
O(L)
O(L)
O(L)
O(L)
O(L)
O(L)
O(L)
O(L)
O(L)
O(L)
O(L)
O(L)
O(L)
O(L)
6-31