Samsung S5PC110 Manual page 1869

S5PC110_UM
3.7.1.2 IIS-BUS Interface Special Registers (IISMOD)
• IISMOD, R/W, Address = 0xE210_0004
• IISMOD, R/W, Address = 0xE2A0_0004
IISMOD Bit
Reserved [31:15]
BLC [14:13]
CDCLKCON [12]
MSS [11]
RCLKSRC [10]
TXR [9:8]
LRP [7]
SDF [6:5]
RFS [4:3]
Reserved. Program to zero.
Bit Length Control Bit Which decides transmission of
8/16 bits per audio channel
00 = 16 Bits per channel
01 = 8 Bits Per Channel
10 = 24 Bits Per Channel
11 = Reserved
Determine codec clock source
0 = Use internal codec clock source
1 = Get codec clock source from external codec chip
* 0 means External CDCLK Input pad enable
(Refer to
Figure 3-2)
IIS master or slave mode select.
0 = Master mode
1 = Slave mode
Select RCLK clock source
0 = PCLK is internal source clock for IIS
1 = SCLK_AUDIO (SCLK_AUDIO1 for I2S1,
SCLK_AUDIO2 for I2S2)
(Refer to
Figure 3-2)
Transmit or receive mode select.
00 = Transmit only mode
01 = Receive only mode
10 = Transmit and receive simultaneous mode
11 = Reserved
Left/Right channel clock polarity select.
0 = Low for left channel and high for right channel
1 = High for left channel and low for right channel
Serial data format.
00 = IIS format
01 = MSB-justified (left-justified) format
10 = LSB-justified (right-justified) format
11 = Reserved
IIS root clock (codec clock) frequency select.
00 = 256 fs, where fs is sampling frequency
01 = 512 fs
10 = 384 fs
11 = 768 fs
Description
3 IIS-BUS INTERFACE
R/W Initial State
R/W 1'b0
R/W 2'b00
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 2'b00
R/W 1'b0
R/W 2'b00
R/W 2'b00
3-18