Samsung S5PC110 Manual page 1844

S5PC110_UM
2.9.1.3 IIS Interface FIFO Control Register (IISFIC, R/W, Address = 0xEEE3_0008)
IISFIC Bit
Reserved [31]
FTX2CNT [30:24]
Reserved [23]
FTX1CNT [22:16]
TFLUSH [15]
FTX0CNT [14:8]
RFLUSH [7]
FRXCNT [6:0]
2.9.1.4 IIS Interface Clock Divider Control Register (IISPSR, R/W, Address = 0xEEE3_000C)
IISPSR Bit
Reserved [31:16]
PSRAEN [15]
Reserved [14]
PSVALA [13:8]
Reserved [7:0]
-
Primary TX FIFO2 data count. FIFO has 64 depth, so value
ranges from 0 to 64.
N: Data count N of FIFO
-
Primary TX FIFO1 data count. FIFO has 64 depth, so value
ranges from 0 to 64.
N: Data count N of FIFO
Primary TX FIFO flush command.
0 = No flush
1 = Flush
Primary TX FIFO0 data count. FIFO has 64 dept, so value
ranges from 0 to 64.
N: Data count N of FIFO
RX FIFO flush command.
0 = No flush
1 = Flush
RX FIFO data count. FIFO has 64 dept, so value ranges from
0 to 64.
N: Data count N of FIFO
-
Pre-scaler (Clock divider) a active.
0 = Inactive
1 = Active
-
Pre-scaler (Clock divider) a division value.
N: Division factor is N+1
-
Description
Description
2 IIS MULTI AUDIO INTERFACE
R/W Initial State
W 0
R 0x00
R 0
R 0x00
R/W 0
R 0x00
R/W 0
R 0x00
R/W Initial State
R 0x00
R/W 0
R 0
R/W 0x00
R 0x00
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