Samsung S5PC110 Manual page 1616

S5PC110_UM
10.1.6 HDMI PHY CONFIGURATION
HDMI PHY is configured using a dedicated I2C, which is only used in TX mode. The address of HDMI PHY is
0x70. The sequence of I2C data is shown in
We recommend following sequence for HDMI PHY configuration
1) Clock path change : CLK_SRC1 [0]_bit (0xE010_0204) is set to "0" (SCLK_PIXEL)
2) HDMI PHY configuration through I2C : refer to below table.
3) HDMI LINK core reset : CORE_RSTOUT [0]_bit (0xFA10_0020) is set to "0" for 100us.
4) PHY ready check
5) Clock path change : CLK_SRC1 [0]_bit (0xE010_0204) is set to "1" (SCLK_HDMIPHY)
Upper sequence is prior to configuration of VP, MIXER and HDMI LINK.
Due to the security policy, below table's configuration is only opened, as shown in
27MHz
(Pixel Clock Ratio)
Addr
8b
0x01 05h
0x02 00h
0x03 D8h
0x04 10h
0x05 1Ch
0x06 30h
0x07 40h
0x08 6Bh
0x09 10h
0x0A 02h
0x0B 52h
0x0C 4Fh
Figure
Figure 10-4
Table 10-2 HDMI PHY Configuration Table for 27MHz OSC_In
27.027MHz
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
10-4.
Sequence of I2C Data
74.176MHz
8b
05h
00h
D8h
10h
9Ch
02h
32h
6Bh
10h
02h
52h
4Fh
Table 10-2.
8b
05h
00h
D8h
10h
9Ch
56h
5Bh
6Bh
10h
01h
52h
BFh
74.25MHz
8b
05h
00h
D8h
10h
1Ch
30h
40h
6Bh
10h
01h
52h
7Fh
10-7