Samsung S5PC110 Manual page 2017

S5PC110_UM
1.1V
VDD 0.6V
ALIVE
VDD /
1.1V
INT
VDD
ARM
3.3V/2.5V/1.8V
VDD
IO
XPWRRGTON
XnRESET
(internal)
RESETn
XXTI
OSC STABLE in Figure 1-4
(VDDINT= 1.1V ± 5%, TA = -25 to 85°C, VDDSYS = 3.3V ± 5%, 2.5V ± 0.25V, 1.8V ± 0.15V)
Parameter
Reset assert time after clock stabilization
OSC
_STABLE
0ns
>
0ns
>
Power-on transition
Figure 1-4
indicates the time required for the oscillator pad to be stabilized.
Table 1-7 Power on Reset Timing Specifications
max
(OSC_STABLE,
PWR_STABLE)
NORMAL mode SLEEP mode Wake-up from SLEEP
Power-On Reset Sequence
Symbol Minimum
t
4
RESW
1 ELECTRICAL DATA
0ns
>
0ns
>
NORMAL mode Power-off transition
Typical Maximum
-
Unit
XTIpll or
EXTCLK
1-10