Samsung S5PC110 Manual page 1724

Risc microprocessor
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S5PC110_UM
10.3.6.55 Tx Related Register (CEC_TX_CTRL, R/W, Address = 0xE1B0_0040)
CEC_TX_CTRL
Reset
Tx_Retrans_Num
-
Tx_BCast
Tx_Start
10.3.6.56 Tx Related Register (CEC_TX_BYTE_NUM, R/W, Address = 0xE1B0_0044)
CEC_TX_BYTE_NUM
Tx_Byte_Num
Bit
[7]
Specifies the CEC Tx reset bit.
0 = No effect
1 = Immediately resets CEC Tx related registers and
state machines to its reset value. Resets to 0 after one
clock.
[6:4]
Specifies the number of retransmissions tried (according
to CEC specification on page CEC-13). Based on the
specification, this value should be set to 5.
[3:2]
Reserved
[1]
Specifies the CEC Tx broadcast message bit. This bit
also specifies the CEC message in
CEC_TX_BUFFER_00~15, which is directly addressed
(addressed to a single device) or broadcast. This bit
determines whether a block transfer is acknowledged or
not (according to ACK scheme in CEC specification
(section CEC 6.1.2))
0 = Directly addressed message
1 = Broadcast message
[0]
Specifies the CEC Tx start bit.
0 = Tx idle
1 = Starts CEC message transfer (Resets to 0 after start)
Bit
[7:0]
Specifies the number of blocks in a message that has to
be sent (1 byte = 1 block in a CEC message).
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Description
Initial State
0
3b001
2b00
0
0
Initial State
0
10-115

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