Samsung S5PC110 Manual page 1663

Risc microprocessor
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S5PC110_UM
10.3.3.33 Audio Related Packet Register (GCP_CON, R/W, Address = 0xFA11_01C0)
GCP_CON
-
ENABLE_1st_VSYNC
ENABLE_2nd_VSYNC
GCP_CON
10.3.3.34 Audio Related Packet Register (GCP_BYTE1, R/W, Address = 0xFA11_01D0)
GCP_BYTE1
GCP_BYTE1
10.3.3.35 Audio Related Packet Register (GCP_BYTE2, R/W, Address = 0xFA11_01D4)
GCP_BYTE2
PP
CD
10.3.3.36 Audio Related Packet Register (GCP_BYTE3, R/W, Address = 0xFA11_01D8)
GCP_BYTE3
-
GCP_BYTE3
Bit
[7:3]
Reserved
[3]
For interlace mode, enable this bit to transfer the GCP
packet on the 1st VSYNC in a frame.
0 = Does not transfer GCP packet
1 = Transfers the GCP packet
On the other hand, for progressive mode, GCP packet is
transferred regardless of this bit, that is, GCP packet in
progressive mode is transferred every vsync if GCP_CON
is 2b1x.
[2]
For interlace mode, enable this bit to transfer the GCP
packet on the 2nd VSYNC in a frame.
0 = Does not transfer GCP packet
1 = Transfers GCP packet
[1:0]
00 = Does not transmit
01 = Transmits once
1x = Transmits every vsync
Transmits GCP packet within 384 cycles after active
vsync.
Bit
[7:0]
Specifies the GCP packet's first data byte. It is either 0x10
(Clear AVMUTE) or 0x01 (Set AVMUTE). For more
information, refer to Table 5-17 of HDMI specification.
Bit
[7:4]
Specifies the Packing Phase (PP). This bit is read only.
[3:0]
Only supports 24bit mode.
0100 : 24 bit
Ohters : Reserved
Bit
[7:1]
Reserved
[0]
Specifies the default state.
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Description
Description
Description
Initial State
5b00000
1b0
1b1
2b00
Initial State
0x00
Initial State
0x0
0x0
Initial State
7b0000000
0
10-54

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