Samsung S5PC110 Manual page 1412

Risc microprocessor
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S5PC110_UM
6.3.2.1.9 RISC2HOST Argument Registers (MFC_RISC2HOST_ARG1, R/W, Address = 0xF170_0048)
MFC_RISC2HOST_ARG1
MFC_RISC2HOST_ARG1
NOTE: When host receives FLUSH_COMMAND_RET, it should check the shared memory at 0x80. 0x8C to figure out the
input and output pointers in each command channel. If [31:16] is not 0xFFFF, a command in CH1 has been flushed.
If [15:0] is not 0xFFFF, a command in CH0 has been flushed.
6.3.2.1.10 RISC2HOST Argument Registers (MFC_RISC2HOST_ARG2, R/W, Address = 0xF170_004C)
MFC_RISC2HOST_ARG2
DISP_ERROR_STATUS
DEC_ERROR_STATUS
6.3.2.1.11 RISC2HOST Argument Registers (MFC_RISC2HOST_ARG3, R/W, Address = 0xF170_0050)
MFC_RISC2HOST_ARG3
MFC_RISC2HOST_ARG3
6.3.2.1.12 RISC2HOST Argument Registers (MFC_RISC2HOST_ARG4, R/W, Address = 0xF170_0054)
MFC_RISC2HOST_ARG4
MFC_RISC2HOST_ARG4
Bit
[31:0]
<OPEN>
An instance ID will be returned
<SYS_INIT>
Firmware memory size will be returned(currently
300KB)
<SEQ_START, FRAME_START, LAST_SEQ,
INIT_BUFFERS, FRAME_START_REALLOC>
A channel ID will be returned
<FLUSH_COMMAND>
[31:16]: Instance ID of CH1
[15:0]: Instance ID of CH0
Bit
[31:16]
Error status for the displayed frame.
Error codes are defined in 0
[15:0]
Error status for the decoded/encoded frame.
Error codes are defined in 0
Bit
[31:0]
<CONTINUE_ENC>
The size of the output stream
Bit
[31:0]
Reserved
Description
Description
Description
Description
6 5BMULTI FORMAT CODEC
Initial State
0
Initial State
0
0
Initial State
0
Initial State
0
6-20

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