Samsung S5PC110 Manual page 1548

S5PC110_UM
8.4.1.5 Video Processor Operation Mode Control Register (VP_MODE, R/W, Address = 0xF910_0010)
VP_MODE
RTQoSTH
Reserved
LINE_SKIP
MEM_MODE
CROMA_EXPANSION
FIELD_ID_AUTO_TOGGLING
2D_IPC
Reserved
Bit
[31:24] RTQoS threshold level configure. The Video
Processor has the 192-depth internal DMA FIFO.
Thus, you can adjust FIFO threshold level.
0 = Not available
1 ~ 191 = Threshold level
192 ~ 255 = Reserved
[23:6] Reserved, read as zero, do not modify
[5] This bit can control DMA operation. If it is set to
'1', DMA skips a line per two lines while it reads
line data.
0 = OFF
1 = ON
[4] 0 = Linear Mode
1 = Tile Mode
(refer to MFC user's manual)
[3] If it is set to '0', only refer to the chrominance of
TOP filed. But set to '1', it uses the chrominance
both TOP and BOTTOM.
0 = Using only C_TOP_PTR
1 = Using both C_TOP_PTR and C_BOT_PTR
[2] 0 = FIELD_ID is defined by user
1 = FIELD_ID is automatically toggled by
V_SYNC
DMA base address is changed by this bit.
Note: VP_FIELD_ID_S register is toggled if this bit
is 1, not VP_FIELD_ID
[1] Interlace to progressive conversion. VP displays
progressive scan as using one filed image
0 = Disables 2D-IPC
1 = Enables 2D-IPC
[0] Reserved. It must be '0'
Description
8 7BVIDEO PROCESSOR
Initial State
0
0
0
0
0
0
0
0
8-14