Samsung S5PC110 Manual page 1725

Risc microprocessor
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S5PC110_UM
10.3.6.57 Tx Related Register (CEC_TX_STATUS_2, R, Address = 0xE1B0_0060)
CEC_TX_STATUS_2
Tx_Wait
Tx_Sending_Start_Bit
Tx_Sending_Hdr_Blk
Tx_Sending_Data_Blk
Tx_Latest_Initiator
-
Bit
[7]
Specifies the CEC Tx signal free time waiting flag bit.
0 = Tx is in other state
1 = CEC Tx waits for signal free time (stops sending
messages after earlier attempts to send message).
[6]
Specifies the CEC Tx start bit sending flag bit.
0 = Tx is in other state
1 = CEC Tx sends a start bit
[5]
Specifies the CEC Tx header block sending flag bit.
0 = Tx is in other state
1 = CEC Tx sends the header block
[4]
Specifies the CEC Tx data block sending flag bit.
0 = Tx is in other state
1 = CEC Tx sends data blocks
[3]
Specifies the CEC Tx last initiator flag bit.
0 = This device is not the latest initiator on the CEC bus
1 = This CEC device is the latest initiator to send a CEC
message; no other CEC device sends a message.
It will be cleared if Rx detects a start bit on the CEC line
or sets Tx_Enable bit of CEC_Tx_Ctrl_0 (that is becomes
a new initiator)
[2:0]
Reserved
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Initial State
0
0
0
0
0
3b000
10-116

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